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The BEE-D exam has 50 questions and runs 1 hours.
These 10 free BEE-D questions are organized by exam domain, so you can see how each part of the Basic Electricity and Electronics - Digital blueprint is tested. Reveal the answer and explanation under each question.
A line test has isolated an 8-bit readback error to one data input stuck LOW. Sending hexadecimal 6D produces decimal 105 at the receiver. With D0 defined as the least significant bit, which input is faulty?
Correct answer: A - D2
A two-digit display is specified to receive one 8421 BCD digit in each four-bit group. Its input is 0100 1011. What should the technician recognize before replacing the display?
Correct answer: C - The right-hand group is not a valid BCD digit.
A wiring drawing shows a six-cavity connector from its mating face, latch at the top. Cavities 1, 2, 3 form the upper row from left to right; 4, 5, 6 form the lower row. A clock conductor belongs in cavity 1. Viewed from the wire-entry face of the same connector, with the latch still at the top, that cavity is at the:
Correct answer: B - Upper right
A digital board runs normally from a low-voltage bench supply but starts resetting when a correctly connected multimeter is inserted in series to measure current. The current fuse is intact and the reading is within range. Voltage at the supply terminals stays normal, but voltage at the board falls; restoring the direct supply connection restores normal operation. Using a second voltmeter, where should the technician measure to test whether the ammeter accounts for the lost voltage?
Correct answer: B - Between the inserted ammeter's selected current-input jack and COM
A function generator has a 50-ohm source resistance. With its load setting at 50 ohms, the display reports 2 V peak-to-peak at zero offset, while a high-impedance scope measures 4 V peak-to-peak centered on zero. The next test requires a 0-to-5 V square wave into a high-impedance clock input. Before connecting that input, which settings should be selected and then verified on the scope?
Correct answer: D - High-Z load; 5 V peak-to-peak; +2.5 V offset
Two patch leads are moved on an unpowered digital trainer. When power is restored, the supply immediately enters an unexpected current-limit condition and a previously cool IC begins heating rapidly. What takes priority?
Correct answer: C - Switch off safely and inspect the changed wiring.
U1 is a two-input NAND gate whose output feeds inverter U2. After the signals settle, both U1 inputs are HIGH, U1's output is HIGH, and U2's output is LOW. Supplies, reference connections, and loading are within specification. Which gate's measured output conflicts with the logic levels at its own inputs?
Correct answer: D - U1 only
A rising-edge-triggered D flip-flop and a falling-edge-triggered JK flip-flop share a clock. Immediately before a HIGH-to-LOW transition, the D device has Q=0 and D=1; the JK device has Q=1, J=0, and K=1. Asynchronous controls are inactive, and all data timing requirements are met. After settling, before any further clock edge, the outputs will be:
Correct answer: A - D-device Q=0; JK-device Q=0
In a standard 555 astable circuit, RA connects the supply to DISCH, RB connects DISCH to the joined TRIG/THRES node, and the timing capacitor connects that node to ground. Only the capacitor is replaced with a larger value. Using the standard RC timing relationships, how does the output change?
Correct answer: D - Frequency decreases; HIGH duty cycle stays the same.
Testing confirms that an SN74HC595 shifts serial data correctly, yet its parallel outputs retain the previous word. Output enable is LOW and reset is inactive. SRCLK has valid pulses, but the storage-register clock RCLK remains LOW. Which change allows the new word to reach the parallel outputs?
Correct answer: A - Apply a rising edge to RCLK after shifting the word.
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